The present invention relates to programmable logic arrays, commonly referred to as programmable gate arrays, and in particular although not exclusively to arrays of the form sometimes referred to as field programmable gate arrays (FPGAs). Such gate arrays offer an alternative to application-specific integrated circuits (ASICs), with the advantage of rapid design implementation.
In one known form of FPGA, "antifuses" are used to create the required logic connections, providing a permanent, one shot, logic structure. These connections are virtually immune to radiation damage or specific event upsets. Another form of FPGA utilises memory, either PROM or EPROM, to store design data which may be downloaded to program the array. Such an arrangement allows the array to be reprogrammed if required, but is liable to loss of data if the power supply is interrupted or when subjected to radiation or any specific event upsets.
In an arrangement disclosed in U.S. Pat. No. 5,198,706, programming cells for FPGAs make use of volatile memory cells to hold programming information, with ferroelectric capacitors provided to reset the states of these volatile memory cells when required, say, after a power-down.